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`timescale 1ns / 1ps
module ADRcounter 
(
                                //% Clock Input
    input                       iClk,
                                //% Asynchronous Reset Input
    input                       iRst_n,
                                
    input                       iStart,
                              
    input                       iStop,

                                //% Output Count value<br>
    output               [31:0]   ovCnt
);

                        //% Internal counter register input equation<br>
reg [31:0]  rvCnt_d;
                        //% Internal counter register Output<br>
reg [31:0]  rvCnt_q;
//////////////////////////////////////////////////////////////////////////////////
// Continous assigments
//////////////////////////////////////////////////////////////////////////////////
assign  ovCnt = rvCnt_q;
//////////////////////////////////////////////////////////////////////////////////
// Sequential logic
//////////////////////////////////////////////////////////////////////////////////
//% Sequential Logic<br>
always @(posedge iClk or negedge iRst_n)
begin
    if(!iRst_n)                                    //Reset?
    begin
        rvCnt_q <= 32'b0;          //Yes, then Count register is 
    end                                         //cleared to 0's.
    else
    begin
        if(iStart && !iStop)                                 //Clock Enable?
        begin
            rvCnt_q <= rvCnt_d;                 //Yes, then the count register is
        end                                     //updated.
        else
        begin
            rvCnt_q <=  rvCnt_q;                //No, then the count register 
        end                                     //doesn't change
    end
end
//////////////////////////////////////////////////////////////////////////////////
// Combinational logic
//////////////////////////////////////////////////////////////////////////////////
//% Combinational Logic<br>
always @*
begin
    rvCnt_d = rvCnt_q + 1'b1;                   //The count increases by 1.
end


endmodule